1. Field of the Invention
The present invention relates to a superconducting memory circuit. More specifically, the present invention relates to a superconducting memory circuit utilizing a superconducting loop composed of a superconductor such as an alloy or oxide.
2. Description of the prior art
One example of such a kind of superconducting memory circuit is proposed by P. Wolf et al. in, for example, an article named as "TWO-JUNCTION JOSEPHSON MEMORY" IBM Technical Disclosure Bulletin Vol. 16 No. 1, page 214, June 1973. A basic circuit diagram is shown in FIG. 1. With reference to FIG. 1, a superconducting memory circuit includes a superconducting loop 1 composed of two superconducting lines 1a and 1b both ends of which are connected to each other; bias lines 2 and 3 are supplying a current to the superconducting liens 1a and 1b; a writing gate 4 formed in one superconducting line 1a; signal lines 5 and 6 for applying a magnetic flux to the writing gate 4; and a detection gate 7 and a read line 8 for detecting existence of a magnetic lux generated in the superconducting loop 1. Each of the writing gate 4 and detection gate 7 is constructed by a Josephson junction or Josephson weak-link.
In a case where a binary "1" is to be written in FIG. 1 circuit, a predetermined current is supplied to the signal lines 5 and 6. Responsively, a magnetic flux is given to the writing gate 4, and therefore, the writing gate 4 causes a voltage drop, that is, is changed in a non-superconducting state. Next, a predetermined current is supplied to the bias lines 2 and 3 such that a current flows in the two superconducting lines 1a and 1b. At this time, a current does not flow in superconducting line 1a because the writing gate 4 causes a voltage drop, and a current below a critical current value flows in only the other superconducting line 1b. In this state, if the current of the signal lines 5 and 6 and the current of the bias lines 2 and 3 are both shut off a ring current or persistent current flows in the superconducting loop 1 such that the magnetic flux is continuously generated within the superconducting loop 1, whereby "1" is written.
In the case where a binary "0" is to be written, in the state where no current is supplied to the bias lines 2 and 3, a predetermined current is supplied to the signal lines 5 and 6. Responsively, the writing gate 4 causes a voltage drop, and therefore, the ring current or persistent current does not flow in the superconducting loop 1, and thus, the magnetic flux of the superconducting loop 1 disappears, whereby "0" is written.
In the case where information which is stored in the superconducting loop 1 in the above described manner is to be read, a predetermined current below a critical current value is supplied to the read line 8 and a predetermined current is supplied to the bias lines 2 and 3. When "1" is stored, since the current from the bias lines 2 and 3 is superposed on the persistent current, the current flows through one of the superconducting lines 1a and 1b becomes larger than the persistent current, and the current flowing in the other superconducting line becomes smaller than the persistent current. Therefore, a magnetic flux larger than that in the case where no current is supplied to the bias lines 2 and 3 is produced. The detection gate 7 causes a voltage drop by this magnet flux, and therefore, the current of the read line 8 becomes smaller. Thus, "1" is read.
When "0" is stored, as described above, no persistent current flows in the superconducting loop 1. At this time, if a predetermined current is supplied to the bias lines 2 and 3, the current is divided in the same amount and flows in the two superconducting lines 1a and 1b, and therefore, no magnetic flux is generated in the superconducting loop 1. Therefore, the detection gate 7 remains in a superconducting state and no change occurs in the current of the read line 8. Thus, "0" is read.
In the conventional superconducting memory circuit as shown in FIG. 1, when "1" is to be written, a predetermined current is supplied once to the signal lines 5 and 6 to cause the writing gate 4 a voltage drop, and a predetermined current is supplied to the bias lines 2 and 3 in this state, and thereafter, the current of the bias lines 2 and 3 and the signal lines 5 and 6 is shut-off. Therefore, operation in the case where "1" is to be written becomes complex, and operation speed is prevented from becoming high.